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h anb it hdd32m72b18rpw url : www.hbe.co.kr 1 hanbit el ectronics co.,ltd. rev 1.0 (august.2002) general description th e hdd32m72d18rpw is a 64 m x 72 bit double data rate(ddr) synchronous dynamic ram high - density memory module. the module consists of eighteen cmos 16 m x 8 bit with 4banks ddr sdram s in 66pin tsop - ii 400mil package s and 2k eeprom i n 8 - pin tssop package on a 184 - pin glass - epoxy. four 0. 1 uf decoupling capacitors are mounted on the printed circuit board in parallel for each ddr sdram. the hdd32m72d18rpw is a di mm ( dual in line memory module ) . synchronous design allows precise cycle cont rol with the use of system clock. data i/o transactions are possible on both edges of dqs . range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications . a ll module components may be powered from a single 2.5 v dc power supply and all inputs and outputs are sstl_2 compatible. features ? p art identification hdd32m72b18rpw C 10a : 1 00 mhz (cl= 2 ) hdd32m72b18rpw C 1 3a : 1 33 mhz (cl= 2 ) hdd32m72b18rpw C 13b : 1 33 mhz (cl= 2.5 ) ? 256mb(32mx72) r egister ed ddr dimm based on 16mx8 ddr sdrsm ? 2.5v 0.2v vdd and vddq power supply ? auto & self refresh capability ( 4k cycles / 64ms) ? all input and output are compatible wi th sstl_2 interface ? data(dq), data strobes and write masks latched on the rising and falling edge s of the clock ? all addresses and control inputs except data(dq), data strobes and data masks latched on the rising edge s of the clock ? mrs cycle with addr ess key programs - latency (access from column address) : 2, 2.5 - burst length : 2, 4, 8 - data scramble : sequential & interleave ? data(dq), data strobes and write masks latched on the rising and falling edge s of the clock ? all addresses and control i nputs except data(dq), data strobes and data masks latched on the rising edge s of the clock ? the used device is 4m x 8bit x 4banks ddr sdram ddr sdram module 256mbyte (32mx72bit), based on 16mx8, 4banks, 4k ref., 184p in - dimm with pll & register part no . h dd32m72d18rpw
h anb it hdd32m72b18rpw url : www.hbe.co.kr 2 hanbit el ectronics co.,ltd. rev 1.0 (august.2002) pin assignment *these pins should be nc in the system which does not support spd pin pin description pin pin description a0~a11 address input vdd power supply(2.5v) ba0~ba1 bank select address vddq power supply for dqs(2.5v) dq0~dq63 data input/output vref power supply for reference cb0~cb7 check b it vddspd serial eeprom power supply(3.3) dqs0~dqs8 data strobe input/output vss ground dm0~dm8 data - in mask sa0~sa2 address in eeprom ck0~/ck0 clock input sda serial data i/o cke0~cke1 clock enable input scl serial clock /cs0~/cs1 chip select input v ddid vdd identification flag /ras row address strobe nc no connection /cas column address strobe pin front pin back pin frontl pin back pin front pin back 1 vref 32 a5 62 v ddq 93 v ss 124 v ss 154 /ras 2 dq0 33 dq24 63 /we 94 dq4 125 a6 155 dq45 3 v ss 34 v ss 64 dq41 95 dq5 126 dq28 156 v ddq 4 dq1 35 dq25 65 /cas 96 v ddq 127 dq29 157 /cs0 5 dqs0 36 dqs3 66 v ss 97 dm0 128 v ddq 158 /cs1 6 dq2 37 a4 67 dqs5 98 dq6 129 dm3 159 dm5 7 v dd 38 v dd 68 dq42 99 dq7 130 a3 160 v ss 8 dq3 39 dq26 69 dq43 100 v ss 131 dq30 161 dq46 9 nc 40 dq27 70 v dd 101 nc 132 v ss 162 dq47 10 /reset 41 a2 71 * /cs2 102 nc 133 dq31 163 * /cs3 11 v ss 42 v ss 72 dq48 103 *a13 134 cb4 164 v ddq 12 dq8 43 a1 73 dq49 10 4 v ddq 135 cb5 165 dq52 13 dq9 44 cb0 74 v ss 105 dq12 136 v ddq 166 dq53 14 dqs1 45 cb1 75 * ck2 106 dq13 137 ck0 167 nc 15 v ddq 46 v dd 76 * /ck2 107 dm1 138 /ck0 168 v dd 16 * ck1 47 dqs8 77 v ddq 108 v dd 139 v ss 169 dm6 17 * /ck1 48 a0 78 dqs6 109 dq14 140 dm8 170 dq54 18 v ss 49 cb2 79 dq50 110 dq15 141 a10 171 dq55 19 dq10 50 v ss 80 dq51 111 cke1 142 cb6 172 v ddq 20 dq11 51 cb3 81 v ss 112 v ddq 143 v ddq 173 nc 21 cke0 52 ba1 82 vddid 113 * ba2 144 cb7 174 dq60 22 v ddq key 83 dq56 114 dq20 key 175 d q61 23 dq16 53 dq32 84 dq57 115 *a12 145 v ss 176 v ss 24 dq17 54 v ddq 85 v dd 116 v ss 146 dq36 177 dm7 25 dqs2 55 dq33 86 dqs7 117 dq21 147 dq37 178 dq62 26 v ss 56 dqs4 87 dq58 118 a11 148 v dd 179 dq63 27 a9 57 dq34 88 dq59 119 dm2 149 dm4 180 v ddq 28 dq18 58 v ss 89 v ss 120 v dd 150 dq38 181 sa0 29 a7 59 ba0 90 nc 121 dq22 151 dq39 182 sa1 30 v ddq 60 dq35 91 sda 122 a8 152 v ss 183 sa2 31 dq19 61 dq40 92 scl 123 dq23 153 dq44 184 vddspd
h anb it hdd32m72b18rpw url : www.hbe.co.kr 3 hanbit el ectronics co.,ltd. rev 1.0 (august.2002) f unctional block diag ram /rcs0 /rcs1 notes: 1. dq - to - i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq/dqs resistors should be 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq strap in (vss): vdd vddq. 5. rs0 and rs1 alternate between the back and front sides of the dimm. 6.address and control resistors should be 22 ohms. /rcs1 /rcs0 a0~a11 ra0~ra11 a0~a1 1
h anb it hdd32m72b18rpw url : www.hbe.co.kr 4 hanbit el ectronics co.,ltd. rev 1.0 (august.2002) pin function descrip tion pin name input function ck, / ck clock ck and ck are differential clock inputs. all address and control input signals are sam - pled on the positive edge of ck and negative edge of ck. output (read) data is referenced to both edges of ck. internal clock signals are derived from ck/ck. cke clock enable cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. deactivating the clock provides precharge power - down and self refresh operation (all banks idle), or active power - down(row active in any bank) . cke is synchronous for all functions except for disabling outputs, which is achieved asynchronously. input buffers, excluding ck, ck and cke are disabled during power - down and self refresh modes, providing low standby power. cke will recognizean lvcmos l ow level prior to vref being stable on power - up. /cs chip select cs enables(registered low) and disables(registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with mult iple banks. cs is considered part of the command code. a0 ~ a1 1 address row/column addresses are multiplexed on the same pins. row address : ra0 ~ ra1 1 , column address : ca0 ~ ca 9 ba0 ~ ba1 bank select address b a0 and ba1 define to which bank an active, read, write or pre - charge command is being applied. / ras row address strobe latches row addresses on the positive going edge of the clk with / ras low. enables row access & precharge. / cas column address strobe latches column addresses on the positive goi ng edge of the clk with / cas low. enables column access. / we write enable enables write operation and row precharge. latches data in starting from / cas, / we active. dq s 0~ 8 data strobe output with read data, input with write data. edge - aligned with read data, cen - tered in write data. used to capture write data. dm0~8 input data mask dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. dm pins include dummy loading internally, to matches the dq and dqs load - ing. dq0 ~ 63 data input/output data inputs/outputs are multiplexed on the same pins. cb0~cb7 check bit check bit input/output pins vddq supply dq power supply : +2.5v 0.2v. vd d supply power supply : +2.5v 0.2v (device specific). vss supply dq ground. vref supply sstl_2 reference voltage. vddspd supply serial eeprom power supply : 3.3v vddid vdd identification flag
h anb it hdd32m72b18rpw url : www.hbe.co.kr 5 hanbit el ectronics co.,ltd. rev 1.0 (august.2002) absolute maximum rat ings parameter symbol rating unte voltage on any pin relative to vss v in , v out - 0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd - 1.0 ~ 3.6 v voltage on v ddq supply relative to vss v ddq - 0.5 ~ 3.6 v storage temperature t stg - 55 ~ +150 c power dissipation p d 18 w short circuit c urrent i os 50 ma notes: operation at above absolute maximum rating can adversely affect device reliability dc operating con ditions ( recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) ) parameter symbol min max unit note supply voltage v dd 2.3 2.7 v i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref v ddq /2 - 50ma v ddq /2 + 50ma v 1 i/o termination voltage (system) v tt v ref C 0.04 v ref + 0.04 v 2 input high voltage v ih (dc) v ref + 0.15 v ref + 0.3 v 4 input lo w voltage v il (dc) - 0.3 v ref - 0.15 v 4 input voltage level, ck and /ck inputs v in (dc) - 0.3 v ddq + 0.3 v input differential voltage , ck and /ck inputs v id (dc) 0.3 v ddq + 0.6 v 3 input crossing point voltage , ck and /ck inputs v ix (dc) 1.15 1.35 v 5 input leakage current i l i - 2 2 ua out put leakage current i oz - 5 5 ua out put high current (v out = 1.95v) i oh - 16.8 ma out put low current (v out = 0.35v) i o l 16.8 ma notes : 1. includes 25mv margin for dc offset on v ref , and a combined tota l of 50mv margin for all ac noise and dc offset on v ref , bandwidth limited to 20mhz. the dram must accommodate dram current spikes on v ref and internal dram noise coupled to v ref , both of which may result in v ref noise. v ref should be de - coupled with an inductance of 3nh. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference be tween the input level on ck and the input level on ck. 4. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. the ac and dc input specifications are relative to a v ref envelop tha t has been bandwidth limited to 200mhz. 5. the value of v ix is expected to equal 0.5* vddq of the transmitting device and must track variations in the dc level of the same. 6. these charactericteristics obey the sstl - 2 class ii standards.
h anb it hdd32m72b18rpw url : www.hbe.co.kr 6 hanbit el ectronics co.,ltd. rev 1.0 (august.2002) capacitance ( v dd = min to max, v ddq = 2.5v to 2.7v, t a = 2 5 c, f = 1 00 mhz ) description symbol min max units input capacitance(a0~a12, ba0~ba1, / ras, / cas ,/we) c in1 - 12 pf input capacitance(cke0,cke1) c in2 - 12 pf input capacitance(/cs0,/cs1) c in3 - 11 pf input capa citance(ck0~/ck1) c in4 - 12 pf input capacitance(dm0~dm8) c in5 - 16 pf d ata & dqs input/output capacitance (dq0 ~ dq 63, dqs0~dqs8 ) c out1 - 16 pf d ata input/output capacitance ( cb0~cb7) ) c out2 - 16 pf d c characteristics (recommended operati ng condition unless otherwise no ted, v dd = 2.5v, t = 25 c) version parameter symbo l test condition - 10a - 13a - 13b unit operating current (one bank active - precharge ) i dd 0 t rc 3 t rc (min) , t c k=100mhz for ddr200,133mhz for ddr266a & ddr266b dq,dm and dqs inputs chan ging twice per clock cycle address and control inputs changing once per clock cycle 1299 1425 1425 ma operating current (one b ank operation) i dd1 one bank open, bl=4,reads - refer to the following page for detailed test condition 1479 1605 1605 ma precharg e power - down standby current i dd2p all banks idle, power - down mode cke v il (max ), t c k=100mhz for ddr200,133mhz for ddr266a & ddr266b v in = v ref for dq,dqs and dm 696 736.5 736.5 ma precharge floating standby current i dd2 f / c s 3 v ih (min ), all banks i dle cke 3 v ih (min) , t c k=100mhz for ddr200,133mhz for ddr266a & ddr266b address and control input s changing once per clock cycle v in = v ref for dq,dqs and dm 831 885 885 ma precharge quiet standby current i dd2 q / c s 3 v ih (min ), all banks idle cke 3 v ih (mi n) , t c k=100mhz for ddr200,133mhz for ddr266a & ddr266b address and other control inputs stable with keeping 3 v ih (min ) or v il (max ) v in = v ref for dq,dqs and dm 786 822 822 active power - down mode standby current i dd 3 p o ne bank active; power - down mode; cke v il (max ), t c k=100mhz for ddr200,133mhz for ddr266a & ddr266b v in = v ref for dq,dqs and dm. 939 975 975 ma active standby current i dd 3 n cs# >= vih(min) , cke>=vih(min) one bank active , active C precharge , trc=trasmax tck = 100mhz for ddr200, 133m hz for ddr266a & ddr266b , dq, dqs and dm inputs changing twice per clock cycle address and other control inputs changing once per clock cycle 1038 1110 1110 ma
h anb it hdd32m72b18rpw url : www.hbe.co.kr 7 hanbit el ectronics co.,ltd. rev 1.0 (august.2002) operating current (burst read) i dd 4r b l = 2, reads, continuous burst one bank open, address an d control inputs changing once per clock cycle, i o ut = 0ma 1839 2055 2055 ma operating current ( bust write) i dd 4w b l = 2, write, continuous burst one bank open, addre ss and control inputs changing once per clock cycle 1839 2100 2100 ma auto refre sh c urrent i dd 5 trc = trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz , distributed refresh 2019 2415 2415 ma normal 336 336 336 self refresh current low power i dd 6 cke =< 0.2v , external clock should be on tck = 100mhz for ddr200, 133mhz for ddr266a & ddr266b 318 318 318 ma operating current (four bank operation) i dd 7a four bank interleaving with bl=4 - refer to the following page for detailed test condition 2919 3315 3315 ma notes: operation at above absolute maximum ratin g can adversely affect device reliability ac operating condition s parameter s tmbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih (ac) vref + 0.3 1 3 input low (logic 0) voltage, dq, dqs and dm signals. v il (ac) vref - 0.3 1 v 3 input differential voltage, ck and ck inputs v id (ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs v ix (ac) 0.5*vddq - 0.2 0.5*vddq+0.2 v 2 notes: 1. vid is the magnitude of the difference between the input level on ck and th e input on ck. 2. the value of v ix is expected to equal 0.5* v ddq of the transmitting device and must track variations in the dc level of the s ame 3. these parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula - tion. the ac and dc input specificatims are refation to a vref envelope that has been bandwidth limited 20mhz. ac operating test conditions parameter value unit note input reference voltage for clock 0.5 * v ddq v input signal maximu m peak swing 1.5 v input signal minimum slew rate 1.0 v input levels( v i h / v i l ) v re f +0.35/ v re f v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see load circuit v
h anb it hdd32m72b18rpw url : www.hbe.co.kr 8 hanbit el ectronics co.,ltd. rev 1.0 (august.2002) a c c haracteristics (these ac charicteristics were tested on the component) ddr200 ddr266a ddr266b - 10a - 13a - 13b parameter symbol min max min max min max unit note row cycle time t rc 70 65 65 ns 1 refresh row cycle time t rfc 80 75 75 ns 1,2 row active time t ras 48 120k 45 120k 45 120k ns 1,2 / ras to / cas delay t rcd 20 20 20 ns 3 row precharge time t rp 20 20 20 ns 3 row active to row active delay t rrd 15 15 15 ns 3 write recovery time t wr 2 2 2 t ck 3 last data in to r ead command t cdlr 1 1 1 t ck 2 col. address to col. address delay t ccd 1 1 1 t ck cl=2.0 10 12 7.5 12 10 12 ns clock cycle time cl=2.5 t ck 12 7.5 12 7.5 12 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low level widt h t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck dqs - out access time from ck/ck t dqsck - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns output data access time from ck/ck t ac - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns data strobe edge to ouput data edge t dqsq - +0.6 - +0.5 - + 0.5 ns read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck data out high impedence time from ck - /ck t hzq - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns 2
h anb it hdd32m72b18rpw url : www.hbe.co.kr 9 hanbit el ectronics co.,ltd. rev 1.0 (august.2002) ck to valid dqs - in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs - in setup time t wpres 0 0 0 ns 3 dqs - in hold time t wpreh 0.25 0.25 0.25 t ck dqs - in falling edge to ck rising - setup time t d ss 0.2 0.2 0.2 t ck dqs - in falling edge to ck rising hold time t dsh 0.2 0.2 0.2 t ck dqs - in high level width t dqs h 0.35 0.35 0.35 t ck dqs - in low level width t dqsl 0.35 0.35 0.35 t ck dqs - in cycle time t dsc 0.9 1.1 0.9 1.1 0.9 1.1 t ck address and control input setup time t is 1.1 0.9 0.9 ns address and control input hold time t ih 1.1 0.9 0.9 ns mod e register set cycle time t mrd 16 15 15 ns dq & dm setup time to dqs t ds 0.6 0.5 0.5 ns dq & dm hold time to dqs t dh 0.6 0.5 0.5 ns dq & dm input pulse width t dipw 2 1.75 1.75 ns power down exit time t pdex 10 10 10 ns exit self ref resh to write command t xsw 116 95 ns exit self refresh to bank active command t xs a 80 75 75 ns exit self refresh to read command t xs r 200 200 200 cycle refresh interval time t ref 7.8 7.8 7.8 us 1 output dqs valid window t q h 0.35 0.35 0.35 t ck dqs write postamble time t w pst 0.25 0.25 0.25 t ck 4 notes : 1. maximum burst refresh of 8. 2. t hzq transitions occurs in the same assess time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving. 3. the specific requirement is that dqs be valid (high - low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on t dqss . 4. the maximum limit for this parameter is not a device limit. the device will operate with a great value for this parameter, but system performance (bus turnaround) will degr ade accordingly.
h anb it hdd32m72b18rpw url : www.hbe.co.kr 10 hanbit el ectronics co.,ltd. rev 1.0 (august.2002) simplified truth tab le command ck e n - 1 ck e n /cs /r a s /c a s /we dm ba 0,1 a10/ ap a11,a12 a9~a0 note register extended mrs h x l l l l x op code 1,2 register mode register set h x l l l l x op code 1,2 auto refresh h 3 entry h l l l l h x x 3 l h h h 3 refresh self refresh exit l h h x x x x x 3 bank active & row addr. h x l l h h x v row address auto precharge disable l 4 read & column address auto precharge e able h x l h l h x v h column address (a0 ~ a9 ) 4 auto precharge disable h l 4 write & column address auto precharge en able h x l h l l x v h column address (a0 ~ a 9 ) 4,6 burst stop h x l h h l x x 7 bank selection v l precharg e all banks h x l l h l x x h x 5 h x x x entry h l l v v v x c lock suspend or active power down exit l h x x x x x x h x x x entry h l l h h h x h x x x precharge power down mode exit l h l v v v x x dm h x v x 8 h x x x no operation command h x l h h h x x (v=valid, x=don't care, h=logic high, l=logic low) notes : 1. op code : operand code a0 ~ a1 2 & ba0 ~ ba 1 : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge st ate. 4. ba0 ~ ba 1 : bank select addresses. if both ba0 and ba1 are "low" at read, write, row active and precharge, bank a is selected. if both ba0 is "low" and ba1 is "high" at read, write, row active and precharge, bank b is selected. if both ba0 is "hig h" and ba1 is "low" at read, write, row active and precharge, bank c is selected. if both ba0 and ba1 are "high" at read, write, row active and precharge, bank d is selected. if a10/ap is "high" at row precharge, ba0 and ba1 is ignored and all banks are se lected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6 . burst stop command is valid at every burst length. 7. dm sampled at the rising and falling edges of the dqs and data - in are masked at the both edges ( write dm latency is 0 )
h anb it hdd32m72b18rpw url : www.hbe.co.kr 11 hanbit el ectronics co.,ltd. rev 1.0 (august.2002) p ackaging information unit : mm < front C side > < rear C side > *** pcb ?? : 1.27 0.08 mm 30.48 0.20 133.35 0.20 30.48 0.20 133.35 0.20
h anb it hdd32m72b18rpw url : www.hbe.co.kr 12 hanbit el ectronics co.,ltd. rev 1.0 (august.2002) o r dering information part number density org. package ref. vcc mode max.frq hdd32m72b18rwp - 10a 256mbyte 32m x 72 184pin dimm 4k 2.5v ddr 100mhz/cl2 hdd32m72b18rw - 13a 256mbyte 32m x 72 184pin dimm 4k 2.5v ddr 100mhz/cl2 hdd32m72 b18rw - 13b 256mbyte 32m x 72 184pin dimm 4k 2.5v ddr 100mhz/cl2

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